/* SPDX-License-Identifier: GPL-2.0+ */
// $Module: reg_G6_PINMUX_REG $
// $RegisterBank Version: v1.0.00 $
// $Author:  $
// $Date: Tue, 28 Feb 2023 09:48:05 AM $
//

//GEN REG ADDR/OFFSET/MASK
#define  G6_PINMUX_REG_REG_I2S0_SCLK  0x0
#define  G6_PINMUX_REG_REG_I2S0_WSI  0x4
#define  G6_PINMUX_REG_REG_I2S0_SDI0  0x8
#define  G6_PINMUX_REG_REG_I2S0_SDI1  0xc
#define  G6_PINMUX_REG_REG_I2S0_SDO  0x10
#define  G6_PINMUX_REG_REG_I2S0_MCLK  0x14
#define  G6_PINMUX_REG_REG_I2S0_SCLK_P_EN   0x0
#define  G6_PINMUX_REG_REG_I2S0_SCLK_P_EN_OFFSET 0
#define  G6_PINMUX_REG_REG_I2S0_SCLK_P_EN_MASK   0x1
#define  G6_PINMUX_REG_REG_I2S0_SCLK_P_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SCLK_PU_SEL   0x0
#define  G6_PINMUX_REG_REG_I2S0_SCLK_PU_SEL_OFFSET 1
#define  G6_PINMUX_REG_REG_I2S0_SCLK_PU_SEL_MASK   0x2
#define  G6_PINMUX_REG_REG_I2S0_SCLK_PU_SEL_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SCLK_PIN_SEL_EN   0x0
#define  G6_PINMUX_REG_REG_I2S0_SCLK_PIN_SEL_EN_OFFSET 4
#define  G6_PINMUX_REG_REG_I2S0_SCLK_PIN_SEL_EN_MASK   0xf0
#define  G6_PINMUX_REG_REG_I2S0_SCLK_PIN_SEL_EN_BITS   0x4
#define  G6_PINMUX_REG_REG_I2S0_SCLK_DRI_SEL   0x0
#define  G6_PINMUX_REG_REG_I2S0_SCLK_DRI_SEL_OFFSET 8
#define  G6_PINMUX_REG_REG_I2S0_SCLK_DRI_SEL_MASK   0xf00
#define  G6_PINMUX_REG_REG_I2S0_SCLK_DRI_SEL_BITS   0x4
#define  G6_PINMUX_REG_REG_I2S0_SCLK_SCT_EN   0x0
#define  G6_PINMUX_REG_REG_I2S0_SCLK_SCT_EN_OFFSET 12
#define  G6_PINMUX_REG_REG_I2S0_SCLK_SCT_EN_MASK   0x1000
#define  G6_PINMUX_REG_REG_I2S0_SCLK_SCT_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SCLK_OEX_EN   0x0
#define  G6_PINMUX_REG_REG_I2S0_SCLK_OEX_EN_OFFSET 13
#define  G6_PINMUX_REG_REG_I2S0_SCLK_OEX_EN_MASK   0x2000
#define  G6_PINMUX_REG_REG_I2S0_SCLK_OEX_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_WSI_P_EN   0x4
#define  G6_PINMUX_REG_REG_I2S0_WSI_P_EN_OFFSET 0
#define  G6_PINMUX_REG_REG_I2S0_WSI_P_EN_MASK   0x1
#define  G6_PINMUX_REG_REG_I2S0_WSI_P_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_WSI_PU_SEL   0x4
#define  G6_PINMUX_REG_REG_I2S0_WSI_PU_SEL_OFFSET 1
#define  G6_PINMUX_REG_REG_I2S0_WSI_PU_SEL_MASK   0x2
#define  G6_PINMUX_REG_REG_I2S0_WSI_PU_SEL_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_WSI_PIN_SEL_EN   0x4
#define  G6_PINMUX_REG_REG_I2S0_WSI_PIN_SEL_EN_OFFSET 4
#define  G6_PINMUX_REG_REG_I2S0_WSI_PIN_SEL_EN_MASK   0xf0
#define  G6_PINMUX_REG_REG_I2S0_WSI_PIN_SEL_EN_BITS   0x4
#define  G6_PINMUX_REG_REG_I2S0_WSI_DRI_SEL   0x4
#define  G6_PINMUX_REG_REG_I2S0_WSI_DRI_SEL_OFFSET 8
#define  G6_PINMUX_REG_REG_I2S0_WSI_DRI_SEL_MASK   0xf00
#define  G6_PINMUX_REG_REG_I2S0_WSI_DRI_SEL_BITS   0x4
#define  G6_PINMUX_REG_REG_I2S0_WSI_SCT_EN   0x4
#define  G6_PINMUX_REG_REG_I2S0_WSI_SCT_EN_OFFSET 12
#define  G6_PINMUX_REG_REG_I2S0_WSI_SCT_EN_MASK   0x1000
#define  G6_PINMUX_REG_REG_I2S0_WSI_SCT_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_WSI_OEX_EN   0x4
#define  G6_PINMUX_REG_REG_I2S0_WSI_OEX_EN_OFFSET 13
#define  G6_PINMUX_REG_REG_I2S0_WSI_OEX_EN_MASK   0x2000
#define  G6_PINMUX_REG_REG_I2S0_WSI_OEX_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDI0_P_EN   0x8
#define  G6_PINMUX_REG_REG_I2S0_SDI0_P_EN_OFFSET 0
#define  G6_PINMUX_REG_REG_I2S0_SDI0_P_EN_MASK   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDI0_P_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDI0_PU_SEL   0x8
#define  G6_PINMUX_REG_REG_I2S0_SDI0_PU_SEL_OFFSET 1
#define  G6_PINMUX_REG_REG_I2S0_SDI0_PU_SEL_MASK   0x2
#define  G6_PINMUX_REG_REG_I2S0_SDI0_PU_SEL_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDI0_PIN_SEL_EN   0x8
#define  G6_PINMUX_REG_REG_I2S0_SDI0_PIN_SEL_EN_OFFSET 4
#define  G6_PINMUX_REG_REG_I2S0_SDI0_PIN_SEL_EN_MASK   0xf0
#define  G6_PINMUX_REG_REG_I2S0_SDI0_PIN_SEL_EN_BITS   0x4
#define  G6_PINMUX_REG_REG_I2S0_SDI0_DRI_SEL   0x8
#define  G6_PINMUX_REG_REG_I2S0_SDI0_DRI_SEL_OFFSET 8
#define  G6_PINMUX_REG_REG_I2S0_SDI0_DRI_SEL_MASK   0xf00
#define  G6_PINMUX_REG_REG_I2S0_SDI0_DRI_SEL_BITS   0x4
#define  G6_PINMUX_REG_REG_I2S0_SDI0_SCT_EN   0x8
#define  G6_PINMUX_REG_REG_I2S0_SDI0_SCT_EN_OFFSET 12
#define  G6_PINMUX_REG_REG_I2S0_SDI0_SCT_EN_MASK   0x1000
#define  G6_PINMUX_REG_REG_I2S0_SDI0_SCT_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDI0_OEX_EN   0x8
#define  G6_PINMUX_REG_REG_I2S0_SDI0_OEX_EN_OFFSET 13
#define  G6_PINMUX_REG_REG_I2S0_SDI0_OEX_EN_MASK   0x2000
#define  G6_PINMUX_REG_REG_I2S0_SDI0_OEX_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDI1_P_EN   0xc
#define  G6_PINMUX_REG_REG_I2S0_SDI1_P_EN_OFFSET 0
#define  G6_PINMUX_REG_REG_I2S0_SDI1_P_EN_MASK   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDI1_P_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDI1_PU_SEL   0xc
#define  G6_PINMUX_REG_REG_I2S0_SDI1_PU_SEL_OFFSET 1
#define  G6_PINMUX_REG_REG_I2S0_SDI1_PU_SEL_MASK   0x2
#define  G6_PINMUX_REG_REG_I2S0_SDI1_PU_SEL_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDI1_PIN_SEL_EN   0xc
#define  G6_PINMUX_REG_REG_I2S0_SDI1_PIN_SEL_EN_OFFSET 4
#define  G6_PINMUX_REG_REG_I2S0_SDI1_PIN_SEL_EN_MASK   0xf0
#define  G6_PINMUX_REG_REG_I2S0_SDI1_PIN_SEL_EN_BITS   0x4
#define  G6_PINMUX_REG_REG_I2S0_SDI1_DRI_SEL   0xc
#define  G6_PINMUX_REG_REG_I2S0_SDI1_DRI_SEL_OFFSET 8
#define  G6_PINMUX_REG_REG_I2S0_SDI1_DRI_SEL_MASK   0xf00
#define  G6_PINMUX_REG_REG_I2S0_SDI1_DRI_SEL_BITS   0x4
#define  G6_PINMUX_REG_REG_I2S0_SDI1_SCT_EN   0xc
#define  G6_PINMUX_REG_REG_I2S0_SDI1_SCT_EN_OFFSET 12
#define  G6_PINMUX_REG_REG_I2S0_SDI1_SCT_EN_MASK   0x1000
#define  G6_PINMUX_REG_REG_I2S0_SDI1_SCT_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDI1_OEX_EN   0xc
#define  G6_PINMUX_REG_REG_I2S0_SDI1_OEX_EN_OFFSET 13
#define  G6_PINMUX_REG_REG_I2S0_SDI1_OEX_EN_MASK   0x2000
#define  G6_PINMUX_REG_REG_I2S0_SDI1_OEX_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDO_P_EN   0x10
#define  G6_PINMUX_REG_REG_I2S0_SDO_P_EN_OFFSET 0
#define  G6_PINMUX_REG_REG_I2S0_SDO_P_EN_MASK   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDO_P_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDO_PU_SEL   0x10
#define  G6_PINMUX_REG_REG_I2S0_SDO_PU_SEL_OFFSET 1
#define  G6_PINMUX_REG_REG_I2S0_SDO_PU_SEL_MASK   0x2
#define  G6_PINMUX_REG_REG_I2S0_SDO_PU_SEL_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDO_PIN_SEL_EN   0x10
#define  G6_PINMUX_REG_REG_I2S0_SDO_PIN_SEL_EN_OFFSET 4
#define  G6_PINMUX_REG_REG_I2S0_SDO_PIN_SEL_EN_MASK   0xf0
#define  G6_PINMUX_REG_REG_I2S0_SDO_PIN_SEL_EN_BITS   0x4
#define  G6_PINMUX_REG_REG_I2S0_SDO_DRI_SEL   0x10
#define  G6_PINMUX_REG_REG_I2S0_SDO_DRI_SEL_OFFSET 8
#define  G6_PINMUX_REG_REG_I2S0_SDO_DRI_SEL_MASK   0xf00
#define  G6_PINMUX_REG_REG_I2S0_SDO_DRI_SEL_BITS   0x4
#define  G6_PINMUX_REG_REG_I2S0_SDO_SCT_EN   0x10
#define  G6_PINMUX_REG_REG_I2S0_SDO_SCT_EN_OFFSET 12
#define  G6_PINMUX_REG_REG_I2S0_SDO_SCT_EN_MASK   0x1000
#define  G6_PINMUX_REG_REG_I2S0_SDO_SCT_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_SDO_OEX_EN   0x10
#define  G6_PINMUX_REG_REG_I2S0_SDO_OEX_EN_OFFSET 13
#define  G6_PINMUX_REG_REG_I2S0_SDO_OEX_EN_MASK   0x2000
#define  G6_PINMUX_REG_REG_I2S0_SDO_OEX_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_MCLK_P_EN   0x14
#define  G6_PINMUX_REG_REG_I2S0_MCLK_P_EN_OFFSET 0
#define  G6_PINMUX_REG_REG_I2S0_MCLK_P_EN_MASK   0x1
#define  G6_PINMUX_REG_REG_I2S0_MCLK_P_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_MCLK_PU_SEL   0x14
#define  G6_PINMUX_REG_REG_I2S0_MCLK_PU_SEL_OFFSET 1
#define  G6_PINMUX_REG_REG_I2S0_MCLK_PU_SEL_MASK   0x2
#define  G6_PINMUX_REG_REG_I2S0_MCLK_PU_SEL_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_MCLK_PIN_SEL_EN   0x14
#define  G6_PINMUX_REG_REG_I2S0_MCLK_PIN_SEL_EN_OFFSET 4
#define  G6_PINMUX_REG_REG_I2S0_MCLK_PIN_SEL_EN_MASK   0xf0
#define  G6_PINMUX_REG_REG_I2S0_MCLK_PIN_SEL_EN_BITS   0x4
#define  G6_PINMUX_REG_REG_I2S0_MCLK_DRI_SEL   0x14
#define  G6_PINMUX_REG_REG_I2S0_MCLK_DRI_SEL_OFFSET 8
#define  G6_PINMUX_REG_REG_I2S0_MCLK_DRI_SEL_MASK   0xf00
#define  G6_PINMUX_REG_REG_I2S0_MCLK_DRI_SEL_BITS   0x4
#define  G6_PINMUX_REG_REG_I2S0_MCLK_SCT_EN   0x14
#define  G6_PINMUX_REG_REG_I2S0_MCLK_SCT_EN_OFFSET 12
#define  G6_PINMUX_REG_REG_I2S0_MCLK_SCT_EN_MASK   0x1000
#define  G6_PINMUX_REG_REG_I2S0_MCLK_SCT_EN_BITS   0x1
#define  G6_PINMUX_REG_REG_I2S0_MCLK_OEX_EN   0x14
#define  G6_PINMUX_REG_REG_I2S0_MCLK_OEX_EN_OFFSET 13
#define  G6_PINMUX_REG_REG_I2S0_MCLK_OEX_EN_MASK   0x2000
#define  G6_PINMUX_REG_REG_I2S0_MCLK_OEX_EN_BITS   0x1
